1. Technical Field of the Present Invention
The present invention generally relates to semiconductor devices, and more particularly, to methods and apparatuses that analyze such semiconductor devices for circuits that can latchup.
2. Description of Related Art
The ever decreasing size of electronic components and their internal structures has resulted in making it easier to either completely destroy or otherwise impair electronic components from latchup. Latchup is when a pnpn structure transitions from a low current high voltage state to a high current low voltage state through a negative resistance region (i.e. forming an S-Type I-V (current/voltage) characteristic).
Latchup is typically understood as occurring within a pnpn structure, or Silicon Controlled Rectifier (SCR) structure. Interestingly enough, these pnpn structures can be intentionally designed, or even unintentionally formed between structures. Hence, latchup conditions can occur within peripheral circuits or internal circuits, within one circuit (intra-circuit) or between multiple circuits (inter-circuit).
Latchup is typically initiated by an equivalent circuit of a cross-coupled pnp and npn transistor. With the base and collector regions being cross-coupled, current flows from one device leading to the initiation of the second (“regenerative feedback”). These pnp and npn elements can be any diffusions or implanted regions of other circuit elements (e.g. P-channel MOSFETs, N-Channel MOSFETs, resistors, etc) or actual pnp and npn bipolar transistors. In CMOS, the pnpn structure can be formed with a p-diffusion in a n-well, and a n-diffusion in a p-substrate (“parasitic pnpn”). In this case, the well and substrate regions are inherently involved in the latchup current exchange between regions.
The condition for triggering a latchup is a function of the current gain of the pnp and npn transistors, and the resistance between the emitter and the base regions. This inherently involves the well and substrate regions. The likelihood or sensitivity of a particular pnpn structure to latchup is a function of spacings (e.g. Base width of the npn and base width of the pnp), current gain of the transistors, substrate resistance and spacings, the well resistance and spacings, and isolation regions.
Many techniques for avoiding latchup conditions in circuits have been developed over the last 30 years. However, the ability to use EDA tools to identify the circuits in which latchup is likely to occur has been limited by time and computer processing constraints.
It would, therefore, be a distinct advantage to have a method and apparatus for quickly and easily identifying circuits in which latchup is likely to occur. The present invention provides such a method and apparatus.